With the launch of its new Ryzen AI 300 series of mobile processors based on the 4 nm ‘Strix Point’ monolithic silicon, AMD is pushing the boundary of today’s processor arms race once again. According to AMD, the new development constitutes ‘a bold leap forward with a new core configuration that could potentially raise the bar for mobile computing performance’. The story doesn’t end there. The significance of Strix Point, however, is more nuanced than that. Let me explain.
At the center of Strix Point is an arrangement that could easily be called an architectural work of art. A silicon that embeds a core mix of 12 CPU cores, but one where not all cores are created equal. This die splits its loyalty: four sturdy ‘Zen 5’ cores and eight tiny ‘Zen 5c’ workers. Not simply a curiosity, the divergence is a strategic play that could open a new door of efficiency and performance.
Using a similar approach, the four ‘Zen 5’ cores on-stage share 1 MB of dedicated L2 cache each and a collective 16 MB L3 cache. There’s plenty of numbers but, being realistic, it is indicative of AMD’s determination to wring every last drop of high-performance computing performance from small boxes.
Even more interesting is the story of the eight ‘Zen 5c’ cores. These retain their own identification numbers, albeit associated with a smaller 8 MB L3 cache shared cluster. Each still has a 1 MB L2 cache, clearly an architectural design philosophy of ‘efficient and powerful, for when you need high IPC without moving big data sets’.
In terms of raw compute capability, the new ‘Zen 5’ and ‘Zen 5c’ cores have roughly comparable IPC efficiencies in simple INT and FP benchmarks, although the ‘Zen 5c’ cores would likely graciously bow out in the more data-intensive streaming situations seen in certain scenarios – a delicacy AMD is probably attempting to hedge with this hybrid configuration.
The work done in determining Stricks Point’s core arrangement results not just in a story, but in a forum for inspiration; it leaps into the realm of thought experiments. The hybrid, with the big IPC efficiency cores mated to their smaller cousins, is a statement on usability and flexibility in the design of processing units for mobile computing.
Prior versions of these more compact ‘Zen 4c’ cores have been unable to sustain higher core voltages that are needed to hit higher frequencies and distancing them even further from the performance of the larger standard cores. If this bottleneck still makes itself apparent with ‘Zen 5c’, it reinforces a very deliberate design choice on AMD’s part to prioritise efficiency but not at the expense of the possibility for the peak performance when it’s most important.
Yet AMD’s Strix Point also constitutes a symbolic milestone in the history of processor design. Its hybrid core configuration might establish a precedent for next-generation technology, wherein power efficiency coexists alongside power consumption to potentially redefine what we should be able to expect from mobile computing.
‘Move’ in the context of processor architecture also means optimal data transfer and computational efficiency within the organisation of the chip itself. AMD’s Strix Point, from the early design thinking through to execution, is the result of a series of fine-grain moves to optimise how this processor allocates resources so that it can adapt to perform at the best possible levels across a diverse mix of workloads. The ‘move’ at the heart of Strix Point’s design philosophy is also a philosophy towards the future of processor design, where energy efficiency and thermal management are balanced with the raw need to deliver power.
But AMD’s Strix Point is really the beginning of something new: it’s going to combine, using new Zen 5 cores and even more energy-efficient Zen 5c cores, to create what AMD hopes will be the ultimate chip of the century. And when it does, the march of processing will continue unabated, while AMD will move us all onto a new frontier.
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